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<div class="header">
  <div class="headertitle"><div class="title">HSEM_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>HW Semaphore HSEM.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:ab568605bc809dfe668847dd7bc89dc8a" id="r_ab568605bc809dfe668847dd7bc89dc8a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab568605bc809dfe668847dd7bc89dc8a">R</a> [32]</td></tr>
<tr class="memitem:adef549dba3b342ce45e57ae1a5c330d0" id="r_adef549dba3b342ce45e57ae1a5c330d0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adef549dba3b342ce45e57ae1a5c330d0">RLR</a> [32]</td></tr>
<tr class="memitem:a69c1de4348244e1e36072b01bbcd0f75" id="r_a69c1de4348244e1e36072b01bbcd0f75"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a69c1de4348244e1e36072b01bbcd0f75">C1IER</a></td></tr>
<tr class="memitem:adbebccb559027a2b858a3c85cc0b224a" id="r_adbebccb559027a2b858a3c85cc0b224a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#adbebccb559027a2b858a3c85cc0b224a">C1ICR</a></td></tr>
<tr class="memitem:a69174dfb50f2b0b06ed8ac999982f3b9" id="r_a69174dfb50f2b0b06ed8ac999982f3b9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a69174dfb50f2b0b06ed8ac999982f3b9">C1ISR</a></td></tr>
<tr class="memitem:a93c90ca6f26ab1e3ae5d027761d41537" id="r_a93c90ca6f26ab1e3ae5d027761d41537"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a93c90ca6f26ab1e3ae5d027761d41537">C1MISR</a></td></tr>
<tr class="memitem:ab6dd340222147610b4c231bbaa29f01d" id="r_ab6dd340222147610b4c231bbaa29f01d"><td class="memItemLeft" align="right" valign="top"><a id="ab6dd340222147610b4c231bbaa29f01d" name="ab6dd340222147610b4c231bbaa29f01d"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><b>Reserved</b> [12]</td></tr>
<tr class="memitem:ab207840b89471c745e4302e2970fed13" id="r_ab207840b89471c745e4302e2970fed13"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab207840b89471c745e4302e2970fed13">CR</a></td></tr>
<tr class="memitem:a41f7be8cb97e115cde34582815fac8c0" id="r_a41f7be8cb97e115cde34582815fac8c0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a41f7be8cb97e115cde34582815fac8c0">KEYR</a></td></tr>
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>HW Semaphore HSEM. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#adbebccb559027a2b858a3c85cc0b224a">&#9670;&#160;</a></span>C1ICR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HSEM_TypeDef::C1ICR</td>
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<p>HSEM Interrupt clear register , Address offset: 104h </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a69c1de4348244e1e36072b01bbcd0f75">&#9670;&#160;</a></span>C1IER</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HSEM_TypeDef::C1IER</td>
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<p>HSEM Interrupt enable register , Address offset: 100h </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a69174dfb50f2b0b06ed8ac999982f3b9">&#9670;&#160;</a></span>C1ISR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HSEM_TypeDef::C1ISR</td>
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<p>HSEM Interrupt Status register , Address offset: 108h </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a93c90ca6f26ab1e3ae5d027761d41537">&#9670;&#160;</a></span>C1MISR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HSEM_TypeDef::C1MISR</td>
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<p>HSEM Interrupt Masked Status register , Address offset: 10Ch </p>

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<a id="ab207840b89471c745e4302e2970fed13" name="ab207840b89471c745e4302e2970fed13"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab207840b89471c745e4302e2970fed13">&#9670;&#160;</a></span>CR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HSEM_TypeDef::CR</td>
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<p>HSEM Semaphore clear register , Address offset: 140h </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a41f7be8cb97e115cde34582815fac8c0">&#9670;&#160;</a></span>KEYR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HSEM_TypeDef::KEYR</td>
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<p>HSEM Semaphore clear key register , Address offset: 144h </p>

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<a id="ab568605bc809dfe668847dd7bc89dc8a" name="ab568605bc809dfe668847dd7bc89dc8a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab568605bc809dfe668847dd7bc89dc8a">&#9670;&#160;</a></span>R</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HSEM_TypeDef::R[32]</td>
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<p>2-step write lock and read back registers, Address offset: 00h-7Ch </p>

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<h2 class="memtitle"><span class="permalink"><a href="#adef549dba3b342ce45e57ae1a5c330d0">&#9670;&#160;</a></span>RLR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t HSEM_TypeDef::RLR[32]</td>
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<p>1-step read lock registers, Address offset: 80h-FCh </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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